This invention generally relates to clocking circuitry and methods of creating timing references on chip. The invention more specifically relates to a slew based clock multiplier which is configured to create any fraction of a master clock relatively precisely. The invention also specifically relates to a method of using such a slew based clock multiplier to create a fraction of a master clock.
Generally, to create a timing reference within a percentage of a single clock cycle, a high frequency clock is used. The clock signal is divided down to a lower frequency, and an edge of a higher frequency clock is used as a reference. However, if one is trying to create a timing reference within the clock period of the maximum on chip clock, an edge of a higher frequency clock does not exist.
Another method of creating a timing reference is to use precision delay cells (i.e., buffers configured to provide a large delay) to delay off the edges of the maximum clock. However, precision delay cells are usually not precise. They have 2:1 variations in delay times, which causes highly variant timing references.
A general object of an embodiment of the present invention is to provide a slew based clock multiplier and a method of using a slew based clock multiplier.
Another object of an embodiment of the present invention is to provide a slew based clock multiplier which is configured to create any fraction of a master clock relatively precisely.
Still another object of an embodiment of the present invention is to provide a slew based clock multiplier which is configured to create a timing reference within a percentage of a single clock cycle without using an edge of a higher frequency clock as a reference.
Another object of an embodiment of the present invention is to provide a method of creating a timing reference within a percentage of a single clock cycle without using an edge of a higher frequency clock as a reference.
Still yet another object of an embodiment of the present invention is to provide a method of creating a timing reference within a percentage of a single clock cycle without using precision delay cells.
Briefly, and in accordance with at least one of the forgoing objects, an embodiment of the present invention provides a slew based clock multiplier which outputs a fraction of a master clock without having to use, as a reference, an edge of a higher frequency clock, and without having to use precision delay cells to delay edges of the master clock. The slew based clock multiplier can be configured to provide such an output as the result of a ratio of input current sources, as the result of a ratio of capacitors in the circuit, or as a result of a combination of the two.